The FortifyIQ family of ultra-high-performance engines is designed to provide ultra-high bandwidth (up to 200 Gbps) along with the strongest protection against Side-Channel Attacks (SCA) and Fault Injection Attacks in the market.

This family includes the AES XTS Engine and AES GCM Engine. The FortifyIQ AES Core is the main building block of all the engines. The Core is resistant to DPA (Differential Power Analysis), SPA (Simple Power Analysis), EMEA (Electromagnetic Emissions Attack), and FIA (Fault Injection Attacks).

The Core passes both the TVLA (Test Vector Leakage Assessment) and the MIA (Mutual Information Analysis) - Leakage Assessment methodologies.

Its resistance against attacks and compliance to the Leakage Assessment methodologies above is proven by theoretical investigation, software simulations using the FortifyIQ analysis toolset (SideChannel Studio for SCA and FaultInjection Studio for FIA), and trials on FPGA implementations.

Side-Channel and Fault Injection Attack Protected
Ultra High Performance Engines

FortifyIQ protection relies on a mathematical algorithm.

FortifyIQ protection relies on a mathematical algorithm while other Industry approaches use combination of multiple technology-dependent methods (e.g. dual-rail, pre charge logic, and masked Look-Up Tables). Each of these methods has its own known weaknesses, that, combined, still may inherit some flaws that are common to all and maintenance of multiple protection methods is costly: every change in a project, as common as re-synthesis, or as impactful as a change in technology, requires retesting and assurance that the combination of methods is still reliable.

The size of FortifyIQ solution is smaller at least by the factor of 5-20.

Since all other Industry protected AES IP cores are slower by factor of 5-20 times, and in Ultra High Performance engines tens of such cores are used in parallel, the size of FortifyIQ solution is smaller at least by the factor of 5-20.

Key Advantages of the FortifyIQ Solution are:

The level of protection against Side-Channel Attacks is agnostic to design environment.

The level of protection against Side-Channel Attacks provided by FortifyIQ IP Engines is agnostic to design environment (synthesis and/or place and route toolset) or process technology changes (e.g. new process node or cell library).

FortifyIP solution is pure soft IP.

FortifyIP solution is pure soft IP – delivered as synthesizable RTL.

Protection is immune to signal glitches and variability inherent.

Protection provided by the FortifyIQ algorithm is immune to signal glitches and variability inherent in the physical design implementation.

Deliverables

  • Verilog RTL source code
  • Documentation
  • Testbench
  • SDC constraints for synthesis
  • Support assistance

Ultra-High-Performance AES XTS Engine

Target Applications
  • Storage, disk encryption
  • Content protection (Set-Top Boxes, SoCs)
  • Automotive
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Ultra-High-Performance AES GCM Engine

Target Applications
  • Communications
  • Secure internet protocols (SSL/TLS, IPSec)
  • Virtual Private Networks (VPN)
  • Content protection (Set-Top Boxes, SoCs)
  • Automotive
Request product sheet

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