The FortifyIQ AES Core is designed to provide the strongest protection against side-channel attacks (SCA) and fault injection attacks (FIA) in the market.

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The Core passes the T-test. The Core passes both the TVLA (Test Vector Leakage Assessment) and the MIA (Mutual Information Analysis) - Leakage Assessment methodologies. Resistance against attacks is proven by theoretical investigation, software simulations using the FortifyIQ analysis toolset (SideChannel Studio + FaultInjection Studio), and trials on FPGA implementations.

Protected AES Core

The FortifyIQ AES Core is resistant to DPA (Differential Power Analysis), SPA (Simple Power Analysis), EMEA (Electromagnetic Emissions Attack), as well as FIA (Fault Injection Attacks).

The Core passes both the TVLA (Test Vector Leakage Assessment) and the MIA (Mutual Information Analysis) - Leakage Assessment methodologies. Its resistance against attacks and compliance to the Leakage Assessment methodologies above is proven by theoretical investigation, software simulations using the FortifyIQ analysis toolset (SideChannel Studio for SCA and FaultInjection Studio for FIA), and trials on FPGA implementations

Key Differentiators

The Fortify Protected AES Core is pure soft IP – delivered as synthesizable RTL.

FortifyIQ protection relies on a mathematical algorithm while other Industry approaches use combination of multiple technology-dependent methods (e.g. dual-rail, pre charge logic, and masked Look-Up Tables). Each of these methods has its own known weaknesses, that, combined, still may inherit some flaws that are common to all and maintenance of multiple protection methods is costly: every change in a project, as common as re-synthesis, or as impactful as a change in technology, requires retesting and assurance that the combination of methods is still reliable.

The level of protection against Side-Channel Attacks.

The level of protection against Side-Channel Attacks provided by FortifyIQ IP Engines is agnostic to design environment (synthesis and/or place and route toolset) or process technology changes (e.g. new process node or cell library).

Flexible design approach.

Flexible design approach allows the user to trade off between area (gate count), performance, frequency, and security level.

Protection provided
by the FortifyIQ algorithm.

Protection provided by the FortifyIQ algorithm is immune to signal glitches and variability inherent in the physical design implementation.

Deliverables

  • Verilog RTL source code
  • Documentation
  • Testbench
  • SDC constraints for synthesis
  • Support assistance

Protected AES Core

Target Applications
  • Communications
  • Automotive
  • Secure internet protocols (SSL/TLS, IPSec)
  • Content protection (Set-Top Boxes, SoCs)
  • Virtual Private Networks (VPN)
  • Storage, disk encryption
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