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Integrate prebuilt side-channel attack protection into your existing system-on-chip.

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FortifyIQ’s IP Cores are prebuilt cells of cryptographic modules that can be integrated into your system-on-chip (SOC) design to mitigate the SOC’s vulnerability to side-channel attacks, such as Differential Power Analysis and Electromagnetic Emission Analysis attacks. Side-channel attacks can extract cryptographic keys from target hardware — thus making the hardware unsecure — by analyzing its power consumption or electromagnetic emission.

By adding FortifyIQ’s IP Cores to an SOC you may reduce or eliminate the SCA (including Fault Injection) threat without spending the time, money, and effort to analyze and redesign the SOC’s existing design.

Side-Channel Attacks
Protected AES Core

The AES IP Core for FPGA, IC, ASIC, and SoC
provides exceptional protection
against side-channel attacks.

Side-Channel Attacks Protected AES Core whitepaper cover

Side-Channel Attacks Protected
AES Core Advantages:

Side-channel attacks protected AES Core for hardware and software icon

Single integrated mathematical method effective for both hardware and software.

Our exclusive protection method is completely unique: it does not rely on costly and complex solutions traditionally used to protect against side-channel attacks. It is as effective for hardware as it is for software.

Side-channel attacks protected AES IP Core with smaller silicon surface area

Smaller silicon surface area.

We do not deploy dual-rail measure or s-boxes in masked LUTs (our s-boxes are shared between encryption and decryption). It allows the decreasing of the necessary silicon area approximately by the factor of four.

AES IP Core with faster microchip performance for protection against side-channel attacks

Faster microchip performance.

Our IP core does not utilize the method of pre-charge logic, thereby reducing the number of clock cycles by the factor of two.

AES Core not affected by place-and-route glitches for top side-channel attacks protection

Not sensitive to place-and-route
glitches and variability.

Our protection performance is not affected by glitches introduced during place-and-route process.

IP Cores with no retesting required for exceptional protection against side-channel attacks

No retesting required.

There is no need to monitor performance or to retest our IP Cores when you make any changes to the environment or the tools used in chip design.

Cost effective side-channel attacks protected AES core

Cost-effective in the long run.

An easy-to-manage single integrated solution oblivious to changes in the environment will decrease your overhead costs.

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