Our exclusive protection method is completely unique: it does not rely on costly and complex technology-dependent approaches traditionally used to protect against side-channel attacks. Our solution is delivered as synthesizable RTL.
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FortiCrypt IP Cores are prebuilt cells of cryptographic modules that can be integrated into your system-on-chip (SoC) design to mitigate the SoC’s vulnerability to security attacks. FortiCrypt IP cores are protected against side-channel attacks and fault injection attacks, such as Differential Power Analysis Attacks, Electromagnetic Emission Analysis Attacks, Differential Fault Attack, Statistical Ineffective Fault attack and others. Side-channel attacks can extract cryptographic keys from target hardware — thus making the hardware unsecure — by analyzing its power consumption or electromagnetic emission. Fault injection attacks can extract keys by injecting functional faults into the hardware and observing the behavior.
By adding FortiCrypt IP Cores to an SoC you may reduce or eliminate the SCA (including Fault Injection) threat without spending the time, money, and effort to analyze and modify your SoC design.
The FortifyIQ family of ultra-high-performance engines is designed to provide
ultra-high bandwidth (up to 200 Gbps) AES calculations along with the strongest
protection against side-channel attacks and fault injection attacks in the industry.
The AES IP Core for FPGA, IC, ASIC, and SoC applications provides
exceptional protection against side-channel and fault injection attacks.
Our exclusive protection method is completely unique: it does not rely on costly and complex technology-dependent approaches traditionally used to protect against side-channel attacks. Our solution is delivered as synthesizable RTL.
It allows the reduction of required silicon area approximately by a factor of 4.
In fact, our design is 5-20 times faster than the best commercial or academic designs.
Our protection performance is not affected by signal glitches and variability exhibited in physical implementation of the design.
There is no need to monitor performance or to retest our IP Cores when you make any changes to the environment or the tools used in chip design.
An easy-to-manage single integrated IP solution that is independent of the design environment will decrease your overhead costs.
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