Our mission is to advance maximum security against side-channel attacks across the entire computing spectrum.
We accomplish this by offering a pre-silicon evaluation toolset built to test hardware designs against Differential Power Analysis and Fault Injection attacks and providing side-channel attack-resistant IP Cores.
A key principle of digital security is to make defense so commonly inexpensive and offense so prohibitively expensive that attacks are no longer viable. However, in the case of side-channel attacks, the economics have a built-in cost differential that favors attackers over defenders.
An attacker only has to break in once to be successful, whereas the defender constantly has to attempt to break in to prove that no potential attack would be successful.
The cost of failure for the attacker is very low: they simply move on to another target. However, if the defender can’t obtain official certification, they have to trash the design and start anew. Worse still, if the defender can’t protect the chip and the chip gets compromised, it spells financial disaster for the manufacturer.
An attacker’s only task is to break in, whereas the defender needs to release a product where the security is but one of many functions.
A defender must spend considerable resources on infrastructure, such as fabrication facilites, and on well-paid staff, whereas an attacker just needs a garage and an oscilloscope.
As one can clearly see, the defender's strategic position is worse than the attacker's in almost all respects, except one: the defender has access to the source design and source code but the hacker doesn’t. Unless defenders use this source access to their advantage, they will continue to play on the field that favors the attackers.
Our vision is to tilt the security playing field in favor of defenders with tools that let them leverage their inherent advantage – their knowledge of the source.