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Secure Cryptography for the Quantum Era
Security Boutique for High‑Assurance Designs
Chip-to-Cloud Security Compliance

Secure, High-Performance Solutions
For Chips, AI, and Compliance

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FortiPQC Post-Quantum Cryptography Implementations
FortiPQC™ Post-Quantum Cryptography Implementations

NIST-standardized post-quantum cryptography, implemented in software and hardware and hardened against side-channel and fault-injection attacks. A unified API ensures seamless HW/SW integration, while crypto-agile, high-assurance designs deliver exceptional performance, power, and area efficiency.

Software Solutions
Hardware Solutions
EDA Tools for Security Assessment and Verification
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EDA Tools for Security Assessment and Verification
Detect and analyze side-channel and fault injection vulnerabilities, pinpointing their sources to the leaking module and even gate. They are continuously updated to include new attacks. For validating the efficiency of in-house developed cryptographic modules both pre- and post-silicon, and to verify the correctness of third-party IP integration — where integration bugs sometimes introduce new vulnerabilities.
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Security Cryptographic HW IP Cores
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FortiAES™, FortiMac™, FortiPKA™, FortiPQC™ and CryptoBox™ Hardware Security IP Cores
Compact, configurable IPs for ASIC/FPGA delivering classical and post-quantum cryptography with the highest security assurance. CryptoBox subsystems integrate easily into any design, while patented protections maintain outstanding performance, power, and area efficiency.
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Root of Trust (RoT)
Root of Trust (RoT) in cybersecurity
Root of Trust (RoT)
FortiTrust™ Quantum-Safe Roots of Trust are compact, highly configurable hardware RoTs from cost-effective, low-power designs for IoT devices to high-performance cloud AI servers with extensive on-the-fly encryption capabilities. SCA/FIA-hardened quantum-safe cryptography with crypto-agile updates, Caliptra-compatible and designed for strong security assurance, they support compliance-driven deployments.
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Cryptographic Software
Cryptographic Software Libraries

High-performance and adaptable, these libraries are optimized for deployed systems as well as budget-conscious or resource-constrained devices. They include post-quantum-safe cryptography, are configurable for various use cases, and perform exceptionally well on edge devices, enabling secure operations even on limited hardware.

Software Cryptography
post-quantum cryptography
Post-Quantum Cryptography Implementations
hardware security
software security solutions
Secure Cryptography for the Quantum Era
Hardware Security Solutions

Leading Security Compliance for Demanding Applications

At FortifyIQ, we deliver powerful, efficient security solutions for extreme
use cases where others fall short. Our technology safeguards against
side-channel (SCA) and fault-injection (FIA) attacks without
compromising on performance, power, or space.

Why Choose FortifyIQ?

Why Choose
FortifyIQ?

  • A Decade of Expertise: Over 10 years
of research defending against advanced physical attacks (e.g., side-channel analysis, fault injection) with silicon-level defenses.
  • Theory + Practice Fusion: Combined academic rigor and industry pragmatism to deliver high-performance, scalable solutions (optimized for speed, power efficiency, usability).
  • Post-Quantum Readiness: FortifyIQ delivers side-channel and fault-attack resistant (SCA/FIA-secure) post-quantum cryptography (PQC) with ultra-low overhead.
  • Mathematical Precision: Algorithm-
    driven security via pure digital logic; compact and efficient, platform-agnostic (ASIC/FPGA).
  • Invincible Resilience: FortifyIQ’s protections are rigorously validated in pre-silicon analysis, FPGA prototyping, silicon testing, as applicable, ensuring systems thrive, even in hostile environments.
software security solutions
Secure Cryptography for the Quantum Era

Maximum security
with minimum power,
latency, and area.

software security solutions
Hardware Security Solutions company

Maximum security with minimum power, latency, and area.

Maximum security
with minimum power,
latency, and area.

Adi Shamir

Professor

Adi Shamir, PhD.

The ‘S’ in RSA
and Turing Prize Winner

FortifyIQ’s solution has the potential of dramatically reducing the cost and delay associated with the manufacturing of DPA-protected devices…

This is an innovative solution to a really important problem, produced by a first-rate team of developers.

software security solutions
Professor Adi Shamir

Professor
Adi Shamir, PhD.

The ‘S’ in RSA and
Turing Prize Winner

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Hardware Security Solutions company
  • FortifyIQ’s solution has the potential of dramatically reducing the cost and delay associated with the manufacturing of DPA-protected devices…

  • This is an innovative solution to a really important problem, produced by a first-rate team of developers.
Hardware Security Solutions
Adi Shamir about FortifyIQ’s solution

Professor

Adi Shamir, PhD.

The ‘S’ in RSA and
Turing Prize Winner

FortifyIQ’s solution has the potential of dramatically reducing the cost and delay associated with the manufacturing of DPA-protected devices…

This is an innovative solution to a really important problem, produced by a first-rate team of developers.

All Insights
Academic Papers
Carry-based Differential Power Analysis (CDPA) and its Application to Attacking HMAC-SHA-2

In this paper, FortifyIQ introduces Carry-based Differential Power Analysis (CDPA), a novel methodology that allows for attacking schemes involving arithmetical addition. This methodology is applied to what is believed to...

In this paper, FortifyIQ introduces Carry-based Differential Power Analysis (CDPA), a novel methodology that allows for attacking schemes involving arithmetical addition. This methodology is applied to what is believed to be the first published full-fledged attack on HMAC-SHA-2 which does not require a profiling stage.

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Modern devices often rely on strong cryptographic keys, yet mathematical strength alone is not enough to ensure security. Attackers increasingly bypass cryptography altogether by exploiting physical leakages through side-channel methods such as Differential Power Analysis (DPA), Differential Electromagnetic Analysis (DEMA), and Fault Injection Analysis (FIA). These attacks are inexpensive to perform, difficult to defend against, and have become a serious threat to contactless smart card systems used in access control, payments, transportation, and digital identity. This paper examines how DEMA attacks compromise smart cards in the real world and introduces a new, cost-effective protection approach that simplifies development while significantly strengthening device security.

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We present Carry-based Differential Power Analysis (CDPA) — a new side-channel attack targeting algorithms that use arithmetic addition. Applied to HMAC-SHA-2, CDPA enables full key recovery from power traces, both in simulation and on FPGA hardware. With as few as
Watch now
Carry-based Differential Power Analysis (CDPA)
Carry-Based Differential Power Analysis and its Application to Attacking HMAC SHA-2
webinar Carry Based Differential Power Analysis
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Academic Papers

Carry-based Differential Power Analysis (CDPA) and its Application to Attacking HMAC-SHA-2

In this paper, FortifyIQ introduces Carry-based Differential Power Analysis (CDPA), a novel methodology that allows for attacking schemes involving arithmetical addition. This...

In this paper, FortifyIQ introduces Carry-based Differential Power Analysis (CDPA), a novel methodology that allows for attacking schemes involving arithmetical addition. This methodology is applied to what is believed to be the first published full-fledged attack on HMAC-SHA-2 which does not require a profiling stage.

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First Full-Fledged
Side Channel Attack
on HMAC-SHA-2

FortifyIQ presents a novel practical template attack on HMAC-SHA-2 intended primarily against its implementations in hardware. Side-channel attacks pose a threat to...

FortifyIQ presents a novel practical template attack on HMAC-SHA-2 intended primarily against its implementations in hardware. Side-channel attacks pose a threat to cryptographic algorithms. HMAC is an important use case of a hash function, in which the input is partially secret and thus unknown to the attacker. Despite a few publications that discuss applications of power analysis techniques to attack HMAC-SHA-2, this is the first generic method that shows a full attack on its hardware implementation.

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RAMBAM: A New Very Compact and Efficient Protection of AES against SC and FI attacks

This is an academic paper describing a protection method for AES which is very efficient, and configurable for any application. It introduces...

This is an academic paper describing a protection method for AES which is very efficient, and configurable for any application. It introduces RAMBAM, an innovative algebraic masking technique designed to protect against side-channel attacks and SIFA1. 

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STORM — Small Table Oriented Redundancy-based SCA Mitigation for AES

STORM effectively solves the long-standing challenge of combining high security against SCA with low gate count and high performance for AES implementations...

STORM effectively solves the long-standing challenge of combining high security against SCA with low gate count and high performance for AES implementations by offering a different tradeoff (memory utilization) that may be preferable to RAMBAM in many practical cases.

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White Papers

Modern devices often rely on strong cryptographic keys, yet mathematical strength alone is not enough to ensure security. Attackers increasingly bypass cryptography altogether by exploiting physical leakages through side-channel methods such as Differential Power Analysis (DPA), Differential Electromagnetic Analysis (DEMA), and Fault Injection Analysis (FIA). These attacks are inexpensive to perform, difficult to defend against, and have become a serious threat to contactless smart card systems used in access control, payments, transportation, and digital identity. This paper examines how DEMA attacks compromise smart cards in the real world and introduces a new, cost-effective protection approach that simplifies development while significantly strengthening device security.

Read more

Side-channel attacks are a pervasive threat to hardware security, particularly in cryptographic systems where they can leak sensitive information. While some leakage can be mitigated through simple countermeasures, advanced attacks require detailed analysis and design-level protections. FortifyIQ’s Side-Channel Studio provides a comprehensive EDA solution for evaluating and strengthening hardware against side-channel attacks. Engineers can validate designs in pre-silicon simulation, on FPGA boards, and post-silicon, gaining the insight and confidence needed to meet certification requirements and ensure robust protection.

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Fault Injection Attacks pose a growing threat to the security of hardware systems, particularly in cryptographic contexts where they can lead to full key recovery. While simple FIAs can often be mitigated through detection mechanisms, cryptographic FIAs — especially ineffective fault attacks — require deeper, design-level countermeasures. FortifyIQ’s Fault Injection Studio addresses this challenge with a comprehensive EDA solution for evaluating and improving algorithmic protections against fault injection attacks.

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Explore FortifyIQ’s AES with RAMBAM protection, providing top-tier defense against side-channel and fault injection attacks.

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Videos

We present Carry-based Differential Power Analysis (CDPA) — a new side-channel attack targeting algorithms that use arithmetic addition. Applied to HMAC-SHA-2, CDPA enables full key recovery from power traces, both in simulation and on FPGA hardware. With as few as
Watch now
Carry-based Differential Power Analysis (CDPA)
Carry-Based Differential Power Analysis and its Application to Attacking HMAC SHA-2
webinar Carry Based Differential Power Analysis
Here we present RAMBAM, our patented novel concept of designing countermeasures against side-channel attacks and SIFA on AES using redundant representations of finite field elements. It enables trade-offs between gate count, maximal frequency, performance, level of robustness to first and
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Redundancy AES Masking Basis for Attack Mitigation
Redundancy AES Masking Basis for Attack Mitigation
Redundancy AES Masking Basis for Attack Mitigation
Attackers can now breach your device for just a few hundred dollars unless robust security measures are in place. Watch our webinar to learn how our solution ensures you no longer have to compromise between security and functionality.
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SEMISRAEL Tech Webinar: Semiconductor Security Simplified
SEMISRAEL Tech Webinar Semiconductor Security Simplified
SEMISRAEL Tech Webinar
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software security solutions

News & Updates

FortifyIQ Partners with Nexus-GT to Expand its Security Market Reach in Israel

The Startup-Nation is increasingly demanding highly efficient, customized classical and post-quantum cryptography. This partnership brings high-assurance system-tailored security to Israel; a “Crypto-Security Boutique.

December 9, 2025

D&R IP SoC Conference

Post-quantum algorithms ML-KEM and ML-DSA, based on Crystals Kyber and Crystals Dilithium, respectively, have been recently standardized by NIST in FIPS 203 and FIPS 204, and are rapidly being adopted worldwide.

December 2, 2025

Interview: Securing the Post-Quantum Era

The industry is rapidly moving toward post-quantum cryptography (PQC). Why does it need protection if it’s supposed to be “quantum-safe”?

November 5, 2025

SemIsrael Expo 2025

Post-quantum algorithms ML-KEM and ML-DSA, based on Crystals Kyber and Crystals Dilithium, respectively, have been recently standardized by NIST in FIPS 203 and FIPS 204, and are rapidly being adopted worldwide. Unfortunately, these algorithms are…

November 1, 2025
SGS certification logo
FortifyIQ AES Algorithm
AVA_VAN.5 Evaluation & Validation Summary
SGS Brightsight Common Criteria Laboratory
“Summary. The leakage analysis (Welch t-test) on over 30 million traces did not show statistically significant first- and second-order differences between trace sets with fixed and random inputs. The template-based DPA analysis, on the pseudo-random trace set for the profiling phase (15 million traces) and on a sub-set of 300k fix input traces for matching phase targeting the first-round S-box output, and template attack on ciphertext, did not indicate any potential information leakage.”
“The results for the soft IP presented in the report were obtained on the TOE which is the basic hardware implementation of the soft IP without additional levels of security (e.g. that are present in a secure silicon layout). Therefore the internal strength of the soft IP itself was evaluated. This indicates that the investigated features and parameters of the soft IP implementation should be robust against SCA and fault injection attacks in different implementations including ASIC. Nevertheless, according to the Common Criteria rules, the strength of the final composite product must be evaluated on its own”
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